This invention relates to a switch-mode power supply (SMPS) apparatus and more particularly to a system for controlling the operation of such a supply.
Switch-mode power supplies (SMPS) are well known in the art. Supplies of this type operate to control power by varying pulses applied to gate the output of the supply and control the switching thereof. The variation employed may involve the duration or width, phase, magnitude, frequency or quantity of the pulse or combinations of these parameters. The output voltage may be controlled as a function of the input voltage, output load variations or other factors. However, in each case it is of critical importance that the relationship among switching pulses be precisely controlled. This control is made more important due to factors associated with non-linearities and temperature drift in the control loop.
For example if a switch mode power supply uses two or more switches which operate in a push-pull fashion to control the application of power to an output stage, it is important not to allow substantial differences in the duty cycle of each switch. This is particularly important where the output stage employs an output transformer as is invariably present since an undesired DC offset in the output transformer may develop causing premature saturation. Thus, when such differences are present and a DC offset develops an unsymmetrical flux density within the transformer will result causing saturation to more rapidly occur in one quadrant or another.
As indicated, switch-mode power supplies are well known and are advantageously employed to decrease size and weight in power supply circuits. Examples of such devices may be found in Principles of Solid State Power Conversion by Ralph E. Tarter, published by Howard W. Sams & Co., Inc., 1985. See for example Chapter 14 entitled "Regulated Power Supplies".
An understanding of push-pull circuitry, may be obtained by reference to U.S. Pat. No. 3,465,231 entitled TRANSFORMERLESS CONVERTER-INVERTER issued on Sept. 2, 1969 to R. L. Hyde. This patent shows an inverter circuit which utilizes a complementary Darlington transistor drive circuit which according to the description provides more efficient operation than the conventional circuit.
U.S. Pat. No. 4,020,361 entitled SWITCHING-MODE POWER CONTROLLER OF LARGE DYNAMIC RANGE issued on Apr. 26, 1977 to L. R. Suelzle. This patent describes the timing sequences of switching the power transistors in a switching mode power supply. The sequence utilizes pulses of short time duration as applied to the transistors to allow the transistor to quickly recover during the changing of states as from On to Off and vice versa.
U.S. Pat. No. 4,095,128 entitled PUSH-PULL SWITCHING CIRCUIT WITH MINORITY CARRIAGE STORAGE DELAY issued on June 13, 1978 to H. Tanigaki. This patent describes another technique for driving a push-pull switching circuit whereby the transistors are controlled by a pair of AND gates. The AND gates are operated by a flip-flop, and each gate is connected to the opposite transistor. The technique prevents simultaneously conduction of the transistors in such a power supply.
Other patents such as U.S. Pat. Nos. 4,213,103 and 4,266,268 describe switching circuits for controlling such power supplies. These circuits are concerned with the Off and On commands to the output switching stages. In any event, as one can ascertain, there is a great deal of prior art concerning switch-mode power supply circuits, and the prior art is cognizant of many of the problems including the above-described problem.
As briefly indicated above, in such power supplies where one employs two or more output switching transistors which operate in a push-pull mode or the like and are conventionally coupled to a drive transformer, it is important not to allow substantial differences in duty cycles to occur. This control must be maintained despite the presence of non-linearities and temperature drift in the circuit. If the duty cycle varies extensively then the drive transformer will appear to have a DC offset. A DC component on a drive signal may cause an nonsymmetrical flux density within the transformer causing premature saturation. Thus reduces the maximum output available with that particular transformer and decreases the efficiency of the power supply. Control which is not substantially independent of non-linearities and drift in the control loop frequently will result in damage to the switching transistors.
If symmetry between the drive input signals is tightly controlled, an overall increase in the efficiency and power density and hence a superior operation of the power supply will result. When digital counting techniques are employed in establishing the mechanism of control, non-linearities and temperature drift in a control loop may be obviated as problems.
It is therefore an object of the present invention to provide apparatus for controlling the duration of a switching signal within a value closely related to a previous value.
It is a further object of the present invention to provide digital control apparatus for maintaining control of a drive signal for switching transistors associated with a drive transformer to assure controlled operation and provide programmable performance.